1. Technical Field
The present invention relates to methods and systems for producing logic on an FPGA. More particularly, the present invention relates to a system for communication between logic on an FPGA that uses multiple master modules and multiple slave modules.
2. Related Art
On a programmable logic device (PLD), such as a field programmable gate array (FPGA), designs can be programmed or instantiated into Configurable Logic Blocks (CLBs) and other resources. The designs can include functional modules such as master modules and slave modules. A master module can provide data to, give a task to, or otherwise control a slave module. Examples of slave modules include direct memory access (DMA) controllers, I/O units, and buffers, such as FIFO buffers. Examples of master modules include processors and other controllers.
A typical embedded system can include multiple master modules and multiple slave modules. Each master module can communicate with one or more slave modules. Each slave module can be accessible by one or more master modules.
Connectivity between various master modules and slave modules can be achieved using shared buses, or by using point-to-point interconnections between the master modules and slave modules. Prior design tools used a single type of connection between master module and slave modules. In the case of a shared bus connection, arbitration logic is typically shared between all masters and is located in the bus. In the case where point-to-point interconnection is used between the master and slaves, arbitration is typically performed on the slave side, thereby aiding simultaneous multi-master transfers. Shared buses typically only allow one transfer to be active at a time. This limits total bandwidth of the system to the bandwidth of the bus. In point-to-point interconnection schemes, however, parallelism of transfers enables the total system bandwidth to be much higher.
Arbitration on the slave side, however generally consumes more logic resources than a centrally arbitrated shared bus. Every slave that is accessed by more than one master implements its own arbitration logic. When there are many such slaves accessed by multiple masters, the logic consumed for arbitration can be large. In the case of a shared bus, however, only one instance of arbitration logic may be required, leading to reduced area requirements. It is desirable to provide a system for arbitration between a master and slave that optimizes the use of resources.